Three-dimensional (3D) semiconductor components designed through monolithic, or sequential, fabrication—the process of vertically stacking two or more semiconductors for wire-bond assembly—present new options for computer design. With the current accelerated growth of mobile and other electronics markets, there have emerged higher product performance expectations, and while 3D components can ultimately be utilized to meet those expectations, they are paired with unique challenges to navigate.
When two or more semiconductors are stacked for wire-bound assembly, the different die (“separated piece, or pieces, of a semiconductor wafer that constitutes a discrete semiconductor or integrated circuit,” from IPC-7091) elements will generally have a small outline. This is a clear and implied advantage of 3D packaging, but there are benefits to the implementation of these components other than taking up less space. Because they utilize a smaller substrate or interposer, the 3D package generally demonstrates lower resistance, inductance, and overall power consumption.
In all, 3D design can help with integrating greater memory onboard CPUs. These benefits, interestingly, can also be said to help extend Moore’s Law.
Moore’s Law is not an actual scientific law but more of an observed trend, named for a prognostic assessment by Gordon Moore. Moore noticed, back in 1965, that transistors were shrinking so fast that every year, twice as many could fit into a chip. While he later adjusted the pace of this trend, in 1975, to a doubling every two years, the same idea was constant: transistors per square inch were exponentially growing.
In fact, this trend has held true throughout the past half-century, and data density has doubled approximately every 18 months. Unfortunately, this may not be the case for much longer, as Moore’s Law is due to die by the early 2020s.
A viable remedy to this imminent change could be the adoption of 3D semiconductor components. If the integration of two-dimensional components has or will soon reach its end, then a logical next step would be three-dimensional fabrication. Whether or not this can actually be considered an expansion of Moore’s Law is a matter of debate, as some are dubbing this idea the end of Moore’s Law and the beginning of 3D integration (see Moore’s law scaling dead by 2021, to be replaced by 3D integration). Regardless, the adoption of 3D semiconductor components offers a vision for the future of semiconductors.
As expected with something that can solve the demise of an assessment for the advancement of computer processors, the design of 3D technology is challenging. With increased demand for product miniaturization and higher product performance expectation, 3D components find luck with the latter but troubles with the former. 3D packaging increasingly is done using large copper pillars, through-silicon vias (TSVs) to vertically connect already-completed chips. However, TSV widths are measureable in micrometers, making them colossal compared to the nanoscale features of today’s chips.
Furthermore, special considerations need to be administered when handling the connectivity between semiconductors, their placement on the substrate, and other concerns. IPC-7091 – Design and Assembly Process Implementation of 3D Components confronts the challenges inherent with 3D components technology design and assembly and offers ways to address those difficulties. It is intended for managers, design/process engineers, and operators who deal with implementing 3D semiconductor packaging, interposer design, substrate design, printed wire board (PWB) design, and board-level assembly, inspection, and repair.
IPC-7091 offers a detailed look into the design of 3D and even two-and-a-half-dimensional (2.5D) packages, which include one or more die mounted on an intermediate imposer and then mounted on the package substrate. The document confronts a host of design considerations, and, to further aid the user, it is abundant with images and other graphics.
IPC-7091 was developed by the 3-D Electronic Packages Subcommittee (B-11) of the Packaged Electronic Components Committee (B-10) of IPC — Association Connecting Electronics Industries.
IPC-7091 – Design and Assembly Process Implementation of 3D Components is available on the ANSI Webstore.
